1. Field of the Invention
This invention relates generally to integrated circuit media access control devices. More specifically, the invention relates to integrated circuits that implement multichannel media access control circuits in a shared memory architecture.
2. Description of the Related Art
Governed by the Institute of Electrical and Electronics Engineers (xe2x80x9cIEEExe2x80x9d) standard 802.3xx, media access control (xe2x80x9cMACxe2x80x9d) devices and circuits have become ubiquitous in network topologies for performing access and error control. MAC devices are responsible in Ethernet networks and other types of local area networks (xe2x80x9cLANsxe2x80x9d) for managing media access, delimiting frames, checking for frame errors, recognizing frame addresses, and direct communication with the network server(s). Available for ordering at the IEEE website, both the draft 802.3xx standards and the adopted 802.3xx standards provide the technical requirements for MAC devices concerning the manner in which they are to be implemented in LANs and in standard and fast Ethernet networks. The IEEE adopted and draft 802.3xx standards are expressly incorporated herein by reference.
On a LAN, the MAC address is a particular computer""s unique hardware number. On an Ethernet LAN, this number is the same as the Ethernet address. When a computer is connected to the Internet, a correspondence table relates the computer""s IP address to the computer""s physical (MAC) address on the LAN. The MAC address is used by the MAC sublayer of the data-link control (xe2x80x9cDLCxe2x80x9d) layer of the particular telecommunications protocol for the system. There is a different MAC sublayer for each physical device type. Needless to say, as the number of physical devices multiplies on the network, a corresponding number of MAC sublayers must be implemented and multiple data channels are therefore created.
Typically, current MAC circuit designs require two dedicated memory elements for each channel of a MAC device, one for the transmit side of the MAC and one for the receive side of the MAC. However, as the number of channels that are found on a MAC integrated circuit increases, the dedicated memory elements for each of the memory elements (usually a FIFO) in each channel of a multi-channel MAC device will lead to a large number of memory elements on the integrated circuit. This large number of memory elements deleteriously impacts the size and the performance of the integrated circuit in a number of ways, not the least of which is an increase in the access time to the internal RAM devices which generally slows down the overall speed of the integrated circuit, and the concomitant increase in the number of MAC sublayers which increases the physical size of the integrated circuit.
Moreover, a common mistake in application specific integrated circuit (ASIC) sizing is that there is a constant area used for every bit of storage. In reality, every memory element contains a certain amount of overhead that includes address decoding, input/output latching and other functionality for the ASIC. As the number of bits in a memory decreases, the percentage of a memory that consists of this overhead increases. Additionally, when a hard placed macro, such as a memory, is placed on a chip, a certain amount of space around the macro is needed for routing overhead. For every side of a macro on a chip, about 50 xcexcm is needed for routing overhead. Thus, for every memory that is placed in a design, an area-penalty is incurred.
There accordingly exists a long-felt but unresolved need in the art for multichannel MAC devices that overcome these and other currently-experienced problems. Such improved devices should reduce the overall size of integrated circuits that implement the MACs, and should minimize the access time to internal RAM devices of the circuit.
The aforementioned problems are solved, and long-felt needs met, by integrated circuits provided in accordance with the present invention. The integrated circuits comprise a plurality of media access control circuits which are capable of receiving and transmitting multiple channels of data according to a clock domain timing sequence internal to each of the media access control circuits. A shared memory element is provided for receiving channel data from more than one of the multiple channels and for requesting that data be fetched from the channels. The memory element is deeply embedded in a FIFO which greatly aids in reducing the physical area of the integrated circuit. Preferably, a multichannel controller is provided for controlling when the data can be stored in the memory element and scheduling the requests from each channel so that the data can be retimed from the clock domain to a host clock domain of the integrated circuit.
The integrated circuits of the present invention provide an improvement over the performance of heretofore-known multichannel MAC devices and greatly reduce the size of prior art integrated circuits that have implemented multichannel MAC devices. By retiming channel data to a host clock domain in accordance with the present invention, channel management efficiency is enhanced over earlier multichannel MAC integrated circuits.
Additionally, the multichannel MAC devices of the present invention greatly reduce the overhead required to implement multi-memory devices. For example, assuming a 16 port MAC device wherein each MAC requires 256 bytes for receive and 256 bytes for transmit. Thus, each MAC would require two 32xc3x9736 RAMs for receive and two more for transmit. Assuming a 0.25 xcexcm fabrication process with a routing overhead of 50 xcexcm, the following table summarizes the area requirements for such a device:
However, in accordance with the invention, eight ports could share one RAM macro; the total number of bits would not change, but the configuration would change. Eight channels together would require two 256xc3x9736 RAMs for receive and two more for transmit. The area requirements for this configuration are as follows:
Thus, the total area drops from 16.66 square millimeters using discrete memories to 6.15 square millimeters using shared memories of the present invention; an area savings of 63%. Such results have not heretofore been achieved in the art.
The inventive integrated circuits also have superior performance characteristics compared to prior MAC devices. Typically, when calculating the speed of operation of a memory structure the placement of memory macros their effects on the capacitive load are mistakenly ignored. As macros are placed farther apart in a design, the capacitive loading on the outputs are increased which increases the time it takes for the RAM to operate. When there are many small RAMs: whose outputs are multiplexed together, the distance between RAMs increases. Thus, for example, multiplexing 8 RAMs together would incur enough of a loading such that half of the delay of the RAM would originate from driving the capacitive load of its outputs. If a 32xc3x9736 memory was driving a load of 5 pf, the access time would be 6.66 ns. As the number of cells decreases, it is easier to place destinations closer to the outputs of the RAMs, which will decrease the loading of the RAMs and therefore increase the performance of the inventive integrated circuits. A 256xc3x9736 RAM driving a load of only 1 pf would have an access time of only 4.5 ns. This is a 32% improvement over prior MAC devices. Again, such results have not heretofore been achieved in the art.
These and other features of the present invention will become apparent from the following detailed description considered in conjunction with the accompanying drawings. It is to be understood, however, that the drawings are designed solely for purposes of illustration and not as a definition of the limits of the invention, for which reference should be made to the appended claims.
Other objects and features of the present invention will become apparent from the following detailed description considered in conjunction with the accompanying drawings. It is to be understood, however, that the drawings are designed solely for purposes of illustration and not as a definition of the limits of the invention, for which reference should be made to the appended claims. It should be further understood that the drawings are not necessarily drawn to scale and that, unless otherwise indicated, they are merely intended to conceptually illustrate the structures and procedures described herein.